Conventionally, a semiconductor device has been known to include two nonvolatile memory cells holding complementary data.
For example, Japanese Patent Laying-Open No. 2008-117510 (PTD 1) describes a semiconductor device comprising: a memory array (19) including a plurality of 1-bit twin cells each composed of electrically rewritable first and second storage devices (MC1 and MC2) holding binary data according to a difference of their flash erase type negative threshold voltages and having different retention characteristics depending on a difference of the binary data held thereby; and a read circuit (SA) for differentially amplifying complementary data output from the first and second storage devices of a twin cell that is selected for a read, and determining information stored in the twin cell.